Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor includes two conductive plates. One plate of each capacitor is typically coupled to a common node with a plate of each of the other capacitors. This plate is referred to as the "cell plate." The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/0) lines through transistors used as switching devices. For each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each memory cell has two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line decoder and to a digit line decoder. The word line decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The digit line decoder selects a digit line pair in response to the digit line address. For a read operation the selected word line activates the access transistors for a given word line address, and data is latched to the digit line pairs.
Inevitably, the fabrication process for a memory device will produce some defective cells. A cell is defective, for example, when the capacitor is not formed properly and acts as a short circuit thus preventing the cell from accurately storing data. These defective cells must be replaced for the memory device to function properly. To this end, designers typically provide a number of extra cells in a memory device. When the device is tested, bad cells are identified and repaired out with the extra cells using known techniques.
Cells in the area of a shorted cell may also be unacceptable for storing data due to the influence of the short circuit on the cell plate voltage. When a word line associated with a bad cell is fired, the shorted capacitor allows the sense amplifier to move the voltage on the cell plate by some amount in the region around the bad cell. Given enough time, the sense amplifier would pull the cell plate toward either the power supply voltage or ground potential. Thus, when the cells that surround a shorted capacitor are restored after a read, the cell plate is not at the correct voltage due to the influence of the short. Once the sense amplifier stops firing, the cell plate returns to its normal voltage during precharge/equilibration procedures. As the cell plate changes voltage, the stored potential on the other plate of the capacitor in each of these cells is also changed. Depending on the amount of movement of the cell plate voltage caused by the short, some adjacent cells may not provide reliable output. Since the amount of cell plate movement is a function of time, current testing techniques use long test periods to determine whether the shorted capacitor eventually will allow the cell plate to move too much so that adjacent cells prove to provide unacceptable results when tested.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved circuit and method for testing a memory device.